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MC74LVX74 Dual D-Type Flip-Flop with Set and Clear
With 5.0 V-Tolerant Inputs
The MC74LVX74 is an advanced high speed CMOS D-type flip-flop. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. The signal level applied to the D input is transferred to O output during the positive going transition of the Clock pulse. Clear (CD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low.
Features http://onsemi.com MARKING DIAGRAMS
14 SOIC-14 D SUFFIX CASE 751A 1 14 TSSOP-14 DT SUFFIX CASE 948G 1 14 SOEIAJ-14 M SUFFIX CASE 965 1 LVX74 ALYWG LVX 74 ALYW G G LVX74G AWLYWW
* * * * * * * * *
1
High Speed: fmax = 145 MHz (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Balanced Propagation Delays Low Noise: VOLP = 0.5 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available*
1
1
VCC 14
CD2 13
D2 12
CP2 11
SD2 10
O2 9
O2 8
A = Assembly Location WL, L = Wafer Lot Y = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
PIN NAMES
1 CD1 2 D1 3 CP1 4 SD1 5 O1 6 O1 7 GND Pins CP1, CP2 D1, D2 CD1, CD2 SD1, SD2 On, On Function Clock Pulse Inputs Data Inputs Direct Clear Inputs Direct Set Inputs Outputs
Figure 1. 14-Lead Pinout (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 3
Publication Order Number: MC74LVX74/D
MC74LVX74
SD1 4 SD D CP CD CD1 1 CD2 13 Q Q 5 6 O1 O1 D2 CP2 SD2 10 SD D CP CD Q Q 9 8 O2 O2
D1 CP1
2 3
12 11
Figure 2. Logic Diagram
INPUTS SDn L H L H H H CDn H L L H H H CPn X X X Dn X X X h l X
OUTPUTS On H L H H L NC On L H H L H NC OPERATING MODE Asynchronous Set Asynchronous Clear Undetermined Load and Read Register Hold
H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low-to-High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Low-to-High Clock Transition; NC = No Change; X = High or Low Voltage Level or Transitions are Acceptable; = Low-to-High Transition; = Not a Low-to-High Transition; For ICC Reasons DO NOT FLOAT Inputs
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Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage -0.5 to +7.0 -0.5 to +7.0 Vout IIK DC Output Voltage -0.5 to VCC +0.5 -20 20 25 50 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation 180 mW _C Tstg Storage Temperature -65 to +150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I
Symbol VCC Vin Parameter Min 2.0 0 0 Max 3.6 5.5 Unit V V V DC Supply Voltage DC Input Voltage Vout TA DC Output Voltage VCC +85 100 Operating Temperature, All Package Types Input Rise and Fall Time -40 0 _C Dt/DV ns/V
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I I I I I IIIIIIIIIII I II I I IIIIIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I I I I I IIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II IIIIIIII I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I IIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) DC ELECTRICAL CHARACTERISTICS
Symbol Symbol tOSHL tOSLH tPLH, tPHL tPLH, tPHL VOH fmax VOL VIH ICC VIL Iin Output-to-Output Skew (Note 1) Maximum Clock Frequency (50% Duty Cycle) Propagation Delay SD or CD to O or O Propagation Delay CP to O or O Quiescent Supply Current Input Leakage Current Low-Level Output Voltage (Vin = VIH or VIL) High-Level Output Voltage (Vin = VIH or VIL) Low-Level Input Voltage High-Level Input Voltage Parameter Parameter IOH = -50mA IOH = -50mA IOH = -4mA VCC = 2.7V VCC = 3.3 0.3V VCC = 3.3 0.3V VCC = 2.7V VCC = 3.3 0.3V VCC = 2.7V VCC = 3.3 0.3V VCC = 2.7V Vin = VCC or GND Vin = 5.5V or GND IOL = 50mA IOL = 50mA IOL = 4mA Test Conditions Test Conditions
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
trec
tsu
tw
tw
th
Minimum Recovery Time, SD or CD to CP
Minimum Hold Time, D to CP
Minimum Setup Time, D to CP
Minimum Pulse Width, CD or SD
Minimum Pulse Width, CP
Parameter
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MC74LVX74
2.7V 3.3V 0.3
2.7V 3.3V 0.3
2.7V 3.3V 0.3
2.7V 3.3V 0.3
2.7V 3.3V 0.3
3 CL = 50pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC V VCC V 3.6 3.6 2.0 3.0 3.0 2.0 3.0 3.0 2.0 3.0 3.6 2.0 3.0 3.6 1.9 2.9 2.58 Min Min 1.5 2.0 2.4 95 60 55 45 TA = 25_C TA = 25C TA = 25C 6.5 5.0 0.5 0.5 8.0 5.5 8.5 6.0 8.5 6.0 8.4 10.9 Typ Typ 145 85 135 60 6.6 9.1 5.7 8.2 7.3 9.8 0.0 0.0 2.0 3.0 Guaranteed Limit 9.7 13.2 0.1 0.1 0.36 10.1 13.6 15.6 19.1 15.0 18.5 Max 0.1 Max 1.5 1.5 2.0 0.5 0.8 0.8 TA = - 40 to 85_C TA = - 40 to 85C TA = - 40 to 85C 1.9 2.9 2.48 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 2.0 2.4 80 50 50 40 10.0 7.0 10.0 7.0 7.5 5.0 0.5 0.5 9.5 6.5 0.1 0.1 0.44 12.0 15.5 18.5 22.0 18.5 22.0 Max 20.0 Max 11.5 15.0 1.0 1.5 1.5 0.5 0.8 0.8 MHz Unit Unit Unit mA mA ns ns ns ns ns ns ns ns V V V V
MC74LVX74
III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII IIII II II IIII I IIIIIIIIIIII IIIIIIIIIIII I I II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
CAPACITIVE CHARACTERISTICS
TA = 25C Typ 4 TA = - 40 to 85C Min Max 10 Symbol Cin Parameter Min Max 10 Unit pF pF Input Capacitance CPD Power Dissipation Capacitance (Note 2) 25
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip-flop). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.3 -0.3 Max 0.5 -0.5 2.0 0.8 Unit V V V V
ORDERING INFORMATION
Device MC74LVX74DR2 MC74LVX74DR2G MC74LVX74DT MC74LVX74DTG MC74LVX74DTR2 MC74LVX74DTR2G MC74LVX74M MC74LVX74MG MC74LVX74MEL MC74LVX74MELG Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Tape & Reel 50 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74LVX74
SWITCHING WAVEFORMS
tw SD or CD VCC 50% tw 1/fmax tPLH O or O 50% VCC CP tPHL O or O GND O or O 50% tPHL 50% VCC tPLH 50% VCC trec 50% VCC GND VCC GND
CP
Figure 3.
Figure 4.
VALID D 50% tsu 50% th
VCC GND VCC GND
CP
Figure 5.
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
Figure 6.
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MC74LVX74
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
TSSOP-14 CASE 948G-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
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EEE CCC EEE CCC
MC74LVX74
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74LVX74/D

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